1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having an MIS (Metal-Insulator-Semiconductor) structure.
2. Description of the Background Art
Improvements in both short channel characteristics and drive capability of MOSFETs are becoming increasingly difficult as device dimensions shrink. As a method to resolve this problem, a replacement sidewall technique has been suggested (in, for example, Japanese Patent Application Laid-open No. 2000-168323). The replacement sidewall technique is a technique for removing a sidewall after deep source/drain (deep S/D) implantation and activation annealing and then performing extension implantation and activation annealing for extension. This technique aims to resolve the problem of a conventional process that heat required for activation of deep S/D is applied also to extensions, and to satisfy both shallow junctions and low parasitic resistance.
In the replacement sidewall process, it is essentially preferable that a sidewall has a SiN/SiO2 multilayer structure. This is because, in the case of a SiO2 single-layer structure, an isolation oxide film also is etched at the time of removal of a sidewall, which arouses concern that an isolation region might recede significantly and thereby junction leakage properties might be worsened. In the case of the SiN/SiO2 multilayer structure, on the other hand, the SiO2 sidewall is thinner than in the case of the single-layer structure, and the gate edge is to be etched as well.
FIGS. 35 to 41 are schematic diagrams illustrating a process sequence of conventional MOSFET fabrication.
<Element Isolation Process>
FIG. 35 shows a cross-section after completion of an element isolation process. On the major surface of a semiconductor substrate 1, an isolation oxide film 2 is formed for element isolation. The isolation oxide film 2 sections an element region of the semiconductor substrate 1. The isolation oxide film 2 may adopt trench isolation. In the structure shown in FIG. 35, well and channel are formed by impurity implantation. The well and channel, however, have no direct relation to the replacement sidewall process and thus not shown herein.
<Gate Insulating Film Formation Process>
The element region of the semiconductor substrate 1 is subjected to gate oxidation.
<Gate Electrode Deposition Process>
A polysilicon layer is formed on the upper surface of a film produced by the gate oxidation.
<Gate Electrode Formation Process>
A resist is applied to a predetermined area of the upper surface of the polysilicon layer and a mask pattern of a gate electrode is transferred and developed. Polysilicon and oxide film are then etched (referred to as “gate etching”) to form a gate electrode 3 as shown in FIG. 36. The gate electrode 3 is formed of a gate insulating film 4 and a polysilicon layer 5.
<Dummy Sidewall Formation Process>
A dummy sidewall 6 (eventually to be removed) is formed as shown in FIG. 37. In the present example, the dummy sidewall 6 of a multilayer structure is formed by depositing an oxide film 7 and then a nitride film 8 on the whole surfaces of the gate electrode 3 and the semiconductor substrate 1 and etching back the films.
<Source and Drain Formation Process>
Source and drain regions 9 (FIG. 38) are formed by ion implantation. This process is performed individually for NMOS and PMOS structures, for example by covering either one of the structures with a resist. Following this, thermal processing is performed to activate implanted impurities.
<Dummy Sidewall Processing Process>
The nitride film 8 of the dummy sidewall 6 shown in FIGS. 37 and 38 is etched using phosphoric acid and completely removed (FIG. 39). After that, the oxide film 7 of the dummy sidewall 6 may be removed and reoxidation (referred to as “gate reoxidation”) may be performed for protection of the gate insulating film 4 at the gate edge.
<Source and Drain Extension Process>
In the structure shown in FIG. 39, source and drain extension regions 10 are formed (FIG. 40). This process is performed individually for NMOS and PMOS structures, for example by covering either one of the structures with a resist. Following this, thermal processing is performed to activate implanted impurities.
<Sidewall Formation Process>
A sidewall 11 is formed as shown in FIG. 41, for example by depositing and etching a nitride film 18 on the whole surface.
<Silicide Process>
A metal such as cobalt or titanium is deposited to form a silicide layer on the upper surfaces of the source and drain regions 9 and the gate electrode 3.
<Interlayer Film Formation Process>
Thereafter, an interlayer film, interconnections and the like are formed according to an ordinary semiconductor integrated circuit manufacturing method.
A sidewall of the SiN/SiO2 multilayer structure has another problem in that Si-exposed source/drain and gate have surface roughness, which is schematically illustrated with triangles in FIGS. 39 to 41. This is because phosphoric acid, which is commonly used in wet etching for removal of a SiN film, removes also a Si film (especially an impurity-doped Si film).
This surface roughness inhibits proper formation of silicide such as CoSi or TiSi and thus can become a cause of an abnormal increase in junction leakage current. Further, if silicide such as CoSi or TiSi is not formed properly and a pin hole is formed in the gate, for example, Co or Ti that was left without silicide formation will reach the gate insulating film, leading to degradation in the reliability of the gate insulating film.